This invention relates to digital processing systems and particularly to a programmable signal processor that is expandable for parallel processing, that provides for the failure of units most liable to have a fault and that performs calculations with a minimum of control elements.
Conventional signal processors may have the capability of adding another arithmetic element but they are not modular in the sense that the same control signals are applied to each arithmetic element. Also, the prior art signal processors have the disadvantage that failure of an arithmetic unit is not correctable without stopping the operation for repairs. Most processors are substantially dependent on a host computer for control and on a bulk memory for storage of data being processed. The waiting time for these external units has been found to substantially reduce the overall speed of processing. It would be a substantial advantage to the art if a processor were provided that was expandable, programmable, operated without substantial waiting time for bulk memory units and that upon failures of the type that were most likely to occur, provided a new configuration that eliminated the effect of the failure.